(a) Field of the Invention
The present invention relates to a process for manufacturing a semiconductor device, and more particularly, it relates to a method for planarization of an interlevel dielectric layer in a semiconductor device having a double- or multi-level interconnection structure (referred to as merely a multilevel interconnection structure hereinafter).
(b) Description of the Related Art
Planarization of interlevel dielectric layers has become a necessary step for fabrication of semiconductor devices having a multilevel metal interconnection structure.
A conventional process for fabricating a semiconductor device having a multilevel interconnection structure will be described with reference to FIGS. 1A and 1B. In FIG. 1A, semiconductor active elements not depicted in the drawing are fabricated within a substrate 301, on which a first silicon oxide layer 302 is deposited in a thickness of about 0.5 .mu.m by chemical vapor deposition (CVD). Then, a first level metal interconnect 303 composed of aluminium is formed in a thickness of about 0.7 .mu.m. Next, a second silicon oxide layer 304 is deposited in a thickness of about 0.7 .mu.m by plasma-enhanced chemical vapor deposition (PECVD), following which an organosilica layer 305 is formed by spin-coating accompanied by a thermal treatment, the configuration at the end of this step being shown in FIG. 1A.
The organosilica layer 305 and the second silicon oxide layer 304 are then etched-back for planarization by a dry etching technology, following which a third silicon oxide layer 306 is formed in a thickness of about 0.5 .mu.m partly on the second silicon oxide layer 304 and partly on the organosilica layer 305 by PECVD. Then, through-holes are opened by a conventional photolithographic etching technology, and a second level metal interconnect 307 composed of aluminium is formed, resulting in a double-level interconnection structure, as shown in FIG. 1B. Such a process is described, for example, in a dissertation beginning at Page 506 of "VMIC, CONF PROC", 1986.
With the conventional semiconductor device as described above, the difference between the thickness of the first level metal interconnect 303 and the thickness of the overlying second silicon oxide layer 304 is small, so that portions of the organosilica layer 305 are left, with the spacing thereof being, for example, above 1.5 .mu.m, in order to assure a planarized surface after the etching-back. In such a configuration of the multilevel interconnection structure, however, there is a problem in which the interlevel dielectric layer is not planarized enough, the third silicon oxide layer 306 is liable to delaminate as shown at a reference numeral 308 or liable to blister due to bumping of residual moisture in the organosilica layer. Hence, the overlying aluminium interconnect 307 suffers from an open-circuit failure due to the poor characteristics of the underlying interlevel dielectric layer, thereby degrading the yield of the semiconductor device having a multilevel interconnection structure.
Besides, since the organosilica layer 305 remains in a wide range within the interlevel dielectric layer, the first level aluminium interconnect 303 is subjected to oxidation at the bottom of a through-hole due to the presence of the organosilica compound. Consequently, the first level aluminium interconnect is degraded in its electric characteristics at the bottom of the through-hole, resulting in a short-circuit failure depending on circumstances. Hence, the yield and the reliability of the semiconductor device having a multilevel structure are reduced.
Some other conventional processes employ a sacrificial layer of a photoresist which is completely removed during etching-back the photoresist and an underlying silicon oxide layer. However, it is difficult to control the etch-rate of the underlying layer with a good accuracy and with a high throughput for achieving a well planarized surface of the interlevel dielectric layer. Consequently, there exists a need for an improved process for fabricating a reliable multilevel interconnection structure by a simple treatment and with a high throughput.